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Winbond Integrated Media Reader W83L519D
W83L519D
W83L519D Datasheet Revision History
Pages Dates Version Version on Web 1 2 3 4 5 6 7 8 02/Jul. 02/Sep. 1.0 1.01 1.0 1.01 1st Release Remove GPIO function and modify recommend circuit. Main Contents
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date: Jul. 2002 Revision 1.0
W83L519D
CONTENT
1 2 2.1 2.2 2.3 2.4 2.5 3 4 4.1 4.2 4.3 4.4 5 GENERAL DESCRIPTION...............................................................................................................3 FUNCTIONS .....................................................................................................................................4 GENERAL ........................................................................................................................................4 SMART CARD INTERFACE .................................................................................................................4 MEMORY STICK INTERFACE..............................................................................................................4 SD MEMORY CARD INTERFACE ........................................................................................................4 PACKAGE ........................................................................................................................................4 PIN CONFIGURATION ....................................................................................................................5 PIN DESCRIPTION ..........................................................................................................................6 BUS INTERFACE...............................................................................................................................6 SMART CARD INTERFACE PINS .........................................................................................................7 MEMORY STICK INTERFACE/SD MEMORY INTERFACE PINS................................................................8 CRYSTAL AND POWER PINS..............................................................................................................9 CONFIGURATION REGISTER ......................................................................................................10
5.1 PLUG AND PLAY CONFIGURATION ...................................................................................................10 5.2 COMPATIBLE PNP..........................................................................................................................10 5.2.1 Extended Function Register ................................................................................................10 5.2.2 Extended Functions Enable Register (EFER) .....................................................................11 5.2.3 Extended Function Index Register (EFIR), Extended Function Data Register (EFDR) ......11 5.3 CONFIGURATION SEQUENCE ..........................................................................................................11 5.3.1 Software programming example ..........................................................................................12 5.4 GLOBAL REGISTERS ......................................................................................................................12 5.5 LOGICAL DEVICE 0 (SMART CARD INTERFACE)................................................................................14 5.6 LOGICAL DEVICE 1 (MEMORY STICK INTERFACE) ............................................................................15 5.7 LOGICAL DEVICE 3 (SD MEMORY INTERFACE) ..............................................................................155 6 7 8 9 ORDERING INSTRUCTION.........................................................................................................176 HOW TO READ THE TOP MARKING.........................................................................................176 PACKAGE DRAWING AND DIMENSIONS ..................................................................................17 THE W83L519D SCHEMATIC .......................................................................................................18
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Publication Release Date: Jul. 2002 Revision 1.0
W83L519D
1
GENERAL DESCRIPTION
W83L519D is Winbond's innovative solution to a new class of storage devices for IA Noetebook, Desktop PC and PC system-related products. It incorporates a security Application: Smart Card Interface and two most promising compact storage interfaces: Memory Stick interface, and Secure Digital Memory Card interface in IT era. To cater boundless IT implementation possibilities, W83L519D can be configured to interface with host through ISA bus. Base on the ISA interface, one Smart Card Interface port and an optional Memory Stick/SD memory Interface ports are provided. The kind of versatility allows user to design very costeffective products in a very flexible way. The whole chip of W83L519D operates at voltage level of 3.3 V except Smart Card Interface port's I/O pins and ISA bus interface that are at 5 V to be compatible with mainstream Smart Card implementations. Advanced power management feature further optimizes power consumption whether in operation or in power down mode. W83L519D comes as a 48-pin LQFP streamline package. Combining with powerful functions, effective power management, and versatile configurability, this integrated media reader offers a perfect approach for design of storage device of IT products. The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation. Information check: http://www.memorystick.org/ The trademarks and intellectual property rights of Secure Digital belong to SD Group. Information check: http://www.sdcard.org/
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
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Publication Release Date: Jul. 2002 Revision 1.0
W83L519D
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2.1
FUNCTIONS
General
Support ISA bus Programmable configuration settings 48 MHz crystal inputs
2.2
Smart Card Interface
ISO-7816 compliant PC/SC T=0, T=1 compliant 16-byte transmitter FIFO and 16-byte receiver FIFO FIFO threshold interrupt to optimize system performance Programmable transmission clock frequency Versatile baud rate configuration UART-like register file structure
2.3
Memory Stick Interface
Memory Stick Standard Format Specifications ver. 1.3 compliant Support interrupt polling transmission Support FIFO threshold interrupt to optimize system performance Automatic clock halt to prevent underrun/overrun 16 MHz interface clock
2.4
SD Memory Card Interface
SD Memory Card Specifications: Part 1 PHYSICAL LAYER SPECIFICATION Version 1.0 Compliant Support interrupt polling transmission Support FIFO threshold interrupt to leverage system performance 24 MHz interface clock
2.5
Package
48-pin LQFP
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Publication Release Date: Jul. 2002 Revision 1.0
W83L519D
3
PIN CONFIGURATION
MSLED/SDLED/SD_WP MSPWR#/SDPWR# VSS
MSCLK/SDCLK MS1/SD1 29 28
36
35 34
33
32 31
30
27
A9 A8 A7 VDD3V A6 A5 A4 A3 A2 A1 A0 IRQB
37 38 39 40 41 42 43 44 45 46 47 48 1
26 25
MS3/SD3 MS4/SD4
MS2/SD2
TC DACK#
DRQ
AEN
W83L519D
24 23 22 21 20 19 18 17 16 15 14 13
MS5/SD5 XIN XOUT SCRST# SCIO SCCLK SCPSNT SCPWR# SCLED VDD D0 D1
10 D4
RESET#
PME# VSS
IRQA
IOR# IOW#
D7
D6 D5
D3 D2
11 12
2 3
4
5 6
7
8 9
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Publication Release Date: Jul. 2002 Revision 1.0
W83L519D
4
Note: INtp3 INts
PIN DESCRIPTION
- 3.3V TTL level input pin - 5V TTL level Schmitt-trigger input pin - 3.3V TTL level Schmitt-trigger input pin - 5V TTL level bi-directional pin with 12 mA drive-sink capability - 5V TTL level bi-directional pin with 24 mA drive-sink capability - 3.3V TTL level bi-directional pin with 24 mA drive-sink capability - 5V output pin with 2 mA drive-sink capability - 5V output pin with 12 mA drive-sink capability - 3.3V output pin with 24 mA drive-sink capability - Open-drain output pin with 12 mA sink capability
INtsp3 I/O12t I/O24t I/O24tp3 O2 O12 O24p3 OD12
4.1
Bus Interface
PIN 4 3 2 1 48 47 46 45 44 43 42 41 39 38 37 I/O INtsp3 INtsp3 INtsp3 O24p3 O24p3 INtp3 INtp3 INtp3 INtp3 INtp3 INtp3 INtp3 INtp3 INtp3 INtp3 FUNCTION Active-low system reset signal. ISA configuration: Active-low signal to enable ISA I/O write accesses. ISA configuration: Active-low signal to enable ISA I/O read accesses. ISA configuration: Interrupt output of Smart Card interface port. ISA configuration: Interrupt output of Memory Stick/SD Memory Card interface port. ISA configuration: Address bit 0. ISA configuration: Address bit 1. ISA configuration: Address bit 2. ISA configuration: Address bit 3. ISA configuration: Address bit 4. ISA configuration: Address bit 5. ISA configuration: Address bit 6. ISA configuration: Address bit 7. ISA configuration: Address bit 8. ISA configuration: Address bit 9.
SYMBOL RESET# IOW# IOR# IRQA IRQB A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
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W83L519D
4.1 Bus Interface (continued.)
SYMBOL AEN
PIN 36
I/O INtp3
FUNCTION ISA configuration: Active-low I/O address enable signal. pulled high in DMA accesses.
It is
TC DACK#
35 34
INtp3 INtp3 O24p3 I/O12t I/O12t I/O12t I/O12t I/O12t I/O12t I/O24t I/O24t OD12
ISA configuration: This pin signals termination of DMA accesses. ISA configuration: DMA acknowledge. validates DMA accesses. This active-low signal
DRQ D7 D6 D5 D4 D3 D2 D1 D0 PME#
33 7 8 9 10 11 12 13 14 5
ISA configuration: DMA request signal. ISA configuration: System data bit 7. ISA configuration: System data bit 6. ISA configuration: System data bit 5. ISA configuration: System data bit 4. ISA configuration: System data bit 3. ISA configuration: System data bit 2. ISA configuration: System data bit 1. ISA configuration: System data bit 0. Active-low PME event.
4.2
Smart Card Interface Pins
PIN 16 I/O O24 O24 INts O2 I/O12t O12 FUNCTION This pin outputs an oscillating clock signal of various frequencies depending on traffic of primary Smart Card interface.
SYMBOL SCLED
SCPWR# SCPSNT
17 18
Primary Smart Card interface power control signal. Primary Smart Card interface card present detection Schmitttrigger input.
SCCLK SCIO SCRST#
19 20 21
Primary Smart Card interface clock output. Primary Smart Card interface data I/O channel. Primary Smart Card interface reset output.
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Publication Release Date: Jul. 2002 Revision 1.0
W83L519D
4.3 Memory Stick Interface/SD Memory Interface Pins
PIN 32 I/O O24p3 FUNCTION MS/SD select = 0, MS function - This pin outputs an oscillating clock signal of various frequencies depending on traffic of primary Memory Stick interface; SDLED O24p3 MS/SD select = 1, SD function - This pin outputs an oscillating clock signal of various frequencies depending on traffic of primary SD memory card interface. SD_WP MSPWR# 31 INts O24p3 MS/SD select = 1, SD function - Write protect input signal. MS/SD select = 0, MS function - This pin is power control signal for primary Memory Stick interface; SDPWR# O24p3 29 O24p3 MS/SD select = 1, SD function - This pin is power control signal for primary SD memory card interface. MSCLK MS/SD select = 0, MS function - This pin is SCLK for primary Memory Stick interface; SDCLK O24p3 28 O24p3 MS/SD select = 1, SD function - This pin is CLK for primary SD memory card interface. MS1 MS/SD select = 0, MS function - This pin is MS1 for primary Memory Stick interface; SD1 I/O24tp3 27 I/O24tp3 MS/SD select = 1, SD function - This pin is SD1 for primary SD memory card interface. MS2 MS/SD select = 0, MS function - This pin is MS2 for primary Memory Stick interface; SD2 I/O24tp3 26 --MS/SD select = 1, SD function - This pin is SD2 for primary SD memory card interface. MS3 MS/SD select = 0, MS function - This pin is MS3 for primary Memory Stick interface; SD3 I/O24tp3 25 INtsp3 MS/SD select = 1, SD function - This pin is SD3 for primary SD memory card interface. MS4 MS/SD select = 0, MS function - This pin is MS4 for primary Memory Stick interface; SD4 I/O24tp3 MS/SD select = 1, SD function - This pin is SD4 for primary SD memory card interface.
SYMBOL MSLED
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Publication Release Date: Jul. 2002 Revision 1.0
W83L519D
4.3 Memory Stick Interface/SD Memory Interface Pins (Continued.)
SYMBOL MS5
PIN 24
I/O ---
FUNCTION MS/SD select = 0, MS function - This pin is MS5 for primary Memory Stick interface;
SD5
I/O24tp3
MS/SD select = 1, SD function - This pin is SD5 for primary SD memory card interface.
4.4
Crystal and Power Pins
PIN 22, 23 FUNCTION Connected to a 48 MHz crystal and function as the working clock for all the media reader interfaces.
SYMBOL XOUT, XIN
VDD3V
40
+3.3V power supply for host interface, MSI/SDI interfaces, and internal core.
VDD VSS
15 6, 30
+5V power supply for Smart Card interface I/O pins. Ground.
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Publication Release Date: Jul. 2002 Revision 1.0
W83L519D
5
5.1
CONFIGURATION REGISTER
Plug and Play Configuration
W83L519D implement compatible PNP protocol to access configuration registers for setting up different types of configurations. There are three Logical Devices (Logical Device 0 to Logical Device 2) in W83L518D/W83L519D which correspond to three major functions: Smart Card Interface (logical device 0), Memory Stick Interface/SD memory Interface (logical device 1), GPIO (logical device 2). Each Logical Device has its own configuration registers (CR30 and above). Host can access those registers by writing an appropriate logical device number into logical device select register at CR7 first.
07h logical device select 30h logical device control 3Fh 40h logical device configuration One set per logical device
global registers
FEh
5.2
5.2.1
Compatible PnP
Extended Function Register
W83L518D/W83L519D provide two methods to enter Extended Function mode (compatible PnP) and access configuration registers dependent on value of HEFRAS (bit 6 of CR26) as follows: HEFRAS 0 1 address and value write 83h to I/O address 2Eh twice write 83h to I/O address 4Eh twice
In Compatible PnP, a specific value (83h) must be written twice to the Extended Function Enable Register (EFER at I/O address 2Eh or 4Eh). Secondly, an index value (02h, 07h-FFh) must be written to the Extended Function Index Register (EFIR, I/O address at 2Eh or 4Eh which is the same as EFER) to identify which configuration register is to be accessed. User can then access the addressed configuration register through the Extended Function Data Register (EFDR, I/O address at 2Fh or 4Fh).
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Publication Release Date: Jul. 2002 Revision 1.0
W83L519D
After programming of the configuration register is completed, another specific value (AAh) should be written to EFER to leave Extended Function mode to prevent inadvertent accesses to those configuration registers. User may write a "1" to bit 5 of CR26 (LOCKREG) to prevent configuration registers from accidental accesses.
5.2.2
Extended Functions Enable Register (EFER)
After a power-on reset, W83L518D/W83L519D enters the default operation mode. A specific value must be programmed into the Extended Function Enable Register (EFER) so that configuration registers can be accessed. On a PC/AT system, its I/O address is 2Eh or 4Eh (as described in previous section).
5.2.3
Extended Function Index Register (EFIR), Extended Function Data Register (EFDR)
After entering Extended Function mode, Extended Function Index Register (EFIR) must be written with an index value (02h, 07h-FEh) to specify which configuration register is to be accessed through Extended Function Data Register (EFDR). EFIR is a write-only register at I/O address 2Eh or 4Eh (as described in section 6.2.1) on a PC/AT system and EFDR is a read/write register at I/O address 2Fh or 4Fh.
5.3
Configuration Sequence
To program configuration registers, specific configuration sequence must be followed: (1) Write 83h to EFER twice to enter Extended Function mode. (2) Select logical device select register by writing 07h to EFIR. (3) Select logical device by writing a value to EFDR. (4) Select control/configuration register by writing its index to EFIR. (5) Access selected control/configuration register through EFDR. (6) Repeat step 4 ~ 5 as needed. (7) Leave Extended Function mode by writing AAh to EFER. Step 2 and step 3 are not necessary for accessing global register (index 00h to 2Fh).
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Publication Release Date: Jul. 2002 Revision 1.0
W83L519D
5.3.1 Software programming example
The following example is written in Intel 8086 assembly language. EFER and EFIR are assumed to be at 2Eh, and EFDR is at 2Fh. Use 4Eh/4Fh instead of 2Eh/2Fh if HEFRAS (bit 6 of CR26) is set. ;----------------------------------------------------------------------------------; Enter Extended Function mode, interruptible double-write | ;----------------------------------------------------------------------------------MOV DX, 2Eh MOV AL, 83h OUT DX, AL OUT DX, AL ;----------------------------------------------------------------------------; Configure logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------MOV DX, 2Eh MOV AL, 07h OUT DX, AL ; point to Logical Device Number Reg. MOV DX, 2Fh MOV AL, 01h OUT DX, AL ; select logical device 1 ; MOV DX, 2Eh MOV AL, F0H OUT DX, AL ; select CRF0 MOV DX, 2Fh MOV AL, 3Ch OUT DX, AL ; update CRF0 with value 3CH ;-----------------------------------------; Exit extended function mode | ;-----------------------------------------MOV DX, 2Eh MOV AL, AAh OUT DX, AL
5.4
Global Registers
CR02 (Default 00h, write only) Bit [7:1]: Reserved. Bit 0: SWRST =0 =1 Normal operation. Software reset.
CR07 (Default 00h) Bit [7:0]: Logical Device Number. CR20 (read only) Bit [7:0]: Device ID number (higher byte). = 71h
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Publication Release Date: Jul. 2002 Revision 1.0
W83L519D
CR21 (read only) Bit [7:0]: Device ID number (lower byte) = 2Xh CR22 (Default 80h) Bit 7: SCPWD =0 =1 Bit 6: MSPWD =0 =1 Bit 5: SDPWD =0 =1 Power down SD memory card interface. No Power down. Power down Memory Stick interface. No Power down. Power down Smart Card interface. No Power down.
Bit [4:0]: Reserved. CR23 (Default 00h) Bit 7: PME_EN. Power management event enable bit. =0 =1 PME_L function is disabled. Enable to issue a low pulse on PME_L when a power management event occurs.
Bit 6: MSPME_EN. Memory Stick interface power management event enable bit. =0 =1 Memory Stick interface power management event is disabled. Enable Memory Stick interface power management event to issue a low pulse on PME_L when PME_EN is also enabled. Bit 5: SDPME_EN. SD memory card interface power management event enable bit. =0 =1 SD memory card interface power management event is disabled. Enable SD memory card interface power management event to issue a low pulse on PME_L when PME_EN is also enabled. Bit 4: SCPME_EN. Smart Card interface power management event enable bit. =0 =1 Smart Card interface power management event is disabled. Enable Smart Card interface power management event to issue a low pulse on PME_L when PME_EN is also enabled. Bit [3:0]: Reserved. CR24 (Default 00h) Bit 7: Reserved. Bit 6: MSPME_STS. Memory Stick interface power management event status bit.
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Publication Release Date: Jul. 2002 Revision 1.0
W83L519D
=0 =1 No Memory Stick interface power management event occurs. Memory Stick interface power management event occurs.
Bit 5: SDPME_STS. SD memory card interface power management event status bit. =0 =1 No SD memory card interface power management event occurs. SD memory card interface power management event occurs.
Bit 4: SCPME_STS. Smart Card interface power management event status bit. =0 =1 No Smart Card interface power management event occurs. No Smart Card interface power management event occurs.
Bit [3:0]: Reserved. CR26 (Default 00h) Bit 7: Reserved Bit 6: HEFRAS, Extended Function Register Address Select. =0 =1 Extended Function Registers are at 2Eh/2Fh. Extended Function Registers are at 4Eh/4Fh.
Bit 5: LOCKREG =0 =1 Enable accesses of Configuration Registers. Disable accesses of Configuration Registers.
Bit [4:0]: Reserved
5.5
Logical Device 0 (Smart Card Interface)
CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: Logical device active bit. =0 Logical device is inactive. =1 Activates the logical device.
CR60, CR61 (Default 0x00, 0x00) These two registers select Smart Card base address [0x100:0xFFF] on 8-byte boundary. CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for Smart Card interface. CRF0 (Default 0x00) Bit [7:1]: Reserved. Bit 0: SCPSNT_POL (Smart Card PreSeNT POLarity). SCPSNT polarity bit. =0 SCPSNT is active high. =1 SCPSNT is active low. 14
Publication Release Date: Jul. 2002 Revision 1.0
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W83L519D
5.6
Logical Device 1 (Memory Stick Interface)
CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: Logical device active bit. = 0: Logical device is inactive. = 1: Activates the logical device. CR60, CR61 (Default 0x00, 0x00) These two registers select MSI base address [0x100:0xFFF] on 8-byte boundary.
CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for MSI. CR74 (Default 0x04) Bit [7:4]: Reserved. Bit [3:0]: These bits select DRQ resource for MSI.
5.7
Logical Device 3 (SD Memory Interface)
Bit [7:1]: Reserved. Bit 0: Logical device active bit. =0 Logical device is inactive. =1 Activates the logical device.
CR30 (Default 0x00)
CR60, CR61 (Default 0x00, 0x00) These two registers select SD Card interface base address [0x100:0xFFF] on 8-byte boundary.
CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for SD interface. CR74 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select DRQ resource for SD interface.
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Publication Release Date: Jul. 2002 Revision 1.0
W83L519D
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
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Publication Release Date: Jul. 2002 Revision 1.0
W83L519D
6
ORDERING INSTRUCTION
PART NO. W83L519D PACKAGE 48-pin LQFP REMARKS
7
HOW TO READ THE TOP MARKING
SMART@IO
W83L519D 114GBSB
1st line: Winbond logo and the SMART@IO Trademark 2nd line: The chip part number. 3rd line: Tracking code 114 G BSB 114: packages made in '01, week 14 G: assembly house ID; O means OSE, G means GR, ... BSB: IC revision
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Publication Release Date: Jul. 2002 Revision 1.0
W83L519D
8
PACKAGE DRAWING AND DIMENSIONS
Package- 48-pin LQFP
H
36
25
37
24
H
48
13
1
12
Symbol
Dimension in inch
Dimension in mm
Min Nom Max
0.002 0.004 0.053 0.055 0.006 0.008 0.004 0.006 0.272 0.276 0.272 0.276 0.014 0.350 0.350 0.018 0.006 0.057 0.010 0.008 0.280 0.280
Min Nom Max
0.05 1.35 0.15 0.10 6.90 6.90 0.35 8.90 8.90 0.45 0.10 1.40 0.20 0.15 7.00 7.00 0.50 9.00 9.00 0.60 1.00 0.15 1.45 0.25 0.20 7.10 7.10 0.65 9.10 9.10 0.75
A A1 A2 b c D E e HD HE L L1 Y 0
0.020 0.026 0.354 0.354 0.024 0.039 0.004 0.358 0.358 0.030
0.10 0 7
0
7
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Publication Release Date: Jul. 2002 Revision 1.0
W83L519D
9
THE W83L519D SCHEMATIC
MSLED/SDLED MSPWCTL#/SDPWCTL# MSCLK/SDCLK MS1/SD1 MS2/SD2 MS3/SD3 MS4/SD4 MS5/SD5 36 35 34 33 32 31 30 29 28 27 26 25 DRQ DACK# TC AEN A[9..0] 1 2 3 4 9 R19 1 4.7K 2 C1 C2 C3 C4 S1 C5 C6 C7 C8 S2 5 6 7 8 10 5VCC SC_VCC SC_SOCKET 1 D4 LED R20 330 2 IRQB IRQA IOR# IOW# A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 37 38 39 40 41 42 43 44 45 46 47 48 2 A9 A8 A7 VDD3V A6 A5 A4 A3 A2 A1 A0 IRQB AEN TC DACK# DRQ MSLED/SDLED MSPWCTL#/SDPWCTL# VSS2 MSCLK/SDCLK MS1/SD1 MS2/SD2 MS3/SD3 MS4/SD4
SC Socket Circuit.
5VCC MOSFET P Q3 1 SC_VCC C6 0.1U R17 4.7K SCRST# SCCLK SCC4 + C7 J2 1U 2 SC_VCC SCLED 1 SC_VCC R11 330 LED R15 1K 2 Q4 NPN D3
SCPWCTL# 1
R12 33 2
SC read/write LED
SC_VCC 1
3VCC
R18 20K
5VCC
Soft start to protect MOSFET(Optional)
SCPSNT
SCIO SCC8
W83519D
MSA/SD5 XIN XOUT SCRST# SCIO SCCLK SCPSNT SCPWRCTL# SCLED VDD D0 D1
24 23 22 21 20 19 18 17 16 15 14 13
XIN XOUT SCRST# SCIO SCCLK SCPSNT SCPWCTL# SCLED D0 D1 D2 D3 D4 D5 D6 D7 D[7:0]
1 2 3 4 5 6 7 8 9 10 11 12
IRQA IOR# IOW# RESET# PME# VSS1 D7 D6 D5 D4 D3 D2
U1 3VCC
RESET# PME#
14 VCC 1 2 X1 R20 48MHz 1M C15 10P U2 48MHZ
2 4 6 8
R5 33 1 SDPWCTL# 1 2
1
3VCC MOSFET P Q1 SD_3VCC RP1
R7 330 R6 4.7K 1 D1 XIN LED J2 10 11 2
1 2 3
8P4R-4.7K C4 0.1U 2 2
1 3 5 7
Soft start to protect MOSFET(Optional)
SD_3VCC R10 D2 330
+ C5 1U SD4 SD3 SDCLK SD2 SD1 SD5 Q2 NPN R14 1M R16 SDLED 1K
1 L1 2.2UH 21 C14 4.7U 2
XOUT Wr_Pt_Vss
Wr_Pt SD4 SD3 Vss2 SDCLK Vdd Vss1 SD2 SD1 SD5
LED
8 7 6 5 4 3 2 1 9
The LC resonance circuit is used to filter base frequency of 3rd overtone crystal. Without SD LED function
R35 2 SDLED 1 4.7K 2 3VCC 1 R34 1K Title
7
GND
SD Socket Circuit.
SD_3VCC 3VCC SD_3VCC S2
OUT
8
C16 10P
R13
10K
SD_SOCKET
inbond
Wr_Pt
Size B Date: WINBOND ELECTRONICS CORP. Document Number W83L519D schematic circuit Monday, June 10, 2002 Sheet 2 of 2 Rev 0.2
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Publication Release Date: Jul. 2002 Revision 1.0
19
W83L519D
The W83L519D Schematic
MS_3VCC
Memory Stick Socket (1) Circuit.
R22 33 MSPWCTL# 1 2 1 Q5 C8 0.1U 2 MOSFET P R23 + C9 4.7K 3VCC MS_3VCC 3VCC 1
R21 330 2 D5 LED J3 1 2 3 4 5 6 7 8 9 10 MS_SOCKET
Winbond Recommended Reader Board <>
R_JP1,2: 1x10 ; 2.0 mm(pitch) R_J1 : 2x5 ; 2.54 mm(pitch)
Soft start to protect MOSFET(Optional)
1U MS1 MS2 MS3 MS4 MS5 MSCLK D6
PIN 1
(R_JP2)
PIN 10
PIN 1
(R_JP1)
PIN 10
MS_3VCC R24
330 LED R26 1K
(OPTION:reserved for power-down)
Q6 NPN
1 R25 C10 200K 0.1U 2
MSLED
1
2
10 PIN 6 PIN 1 2 (R_J1) 5
MS read/write LED
Extension Connectors
3VCC JP1 SD1 SD2 SD3 SD4 SD5 SDCLK SDPWR# SDLED SD1 SD2 SD3 SD4 SD5 SDCLK SDPWR# SDLED 1 2 3 4 5 6 7 8 9 10 3VCC 1 1 SD1 R2 1M
Note 1:These IRQ signals (IRQA,IRQB) can tie to IRQX(IRQ3,4,...) of ISA bus or
compatible ones.
Note 2:These DMA signals (DRQ,DACK#) can tie to which pair (DRQ1,DACK1#,...) of
ISA bus or compatible ones.(except 16 bits DMA transaction)
R1 R SD4 2 2
Note 3:The RESET# should be connected with a low asserted signal.(active low) Note 4:There is either function of SD and MS can be used and depeneded on the
design.
3VCC 1 1 MS1 R4 1M
Note 5:If any of SC or MS/SD function isn't intened to use, signal SCPSNT should
be tied to a pull-down resitor and MS4/SD4 to a pull-high one. (recommended: 4.7K Ohm )
R3 1M 3VCC MS1 MS2 MS3 MS4 MS5 MSCLK MSPWR# MSLED MS1 MS2 MS3 MS4 MS5 MSCLK MSPWR# MSLED JP2 1 2 3 4 5 6 7 8 9 10 MS4
Note 6:The
trade marks and intellectual property rights of Memory Stick belong to SONY Corporation. Information check: http://www.memorystick.org
2
2
1
SCPSNT R5 1M
5VCC JP3 SCPWR# SCC4 SCIO SCCLK SCPWR# SCC4 SCIO SCCLK 1 2 3 4 5 6 7 8 9 10 SCRST# SCLED SCC8 SCPSNT SCRST# SCLED SCC8 SCPSNT Title Size B Date: WINBOND ELECTRONICS CORP. Document Number W83L519D schematic circuit Monday, June 10, 2002 Sheet 2 of 2 Rev 0.2 2
inbond
HEADER 5X2
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
Publication Release Date: Jul. 2002 Revision 1.0
20
W83L519D
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2727 North First Street San Jose, California 95134 TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
9F, No. 480, Rueiguang Road, Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners.
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
21
Publication Release Date: Jul. 2002 Revision 1.0

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